Self-aligned epi contact flow

ABSTRACT

Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of U.S. Provisional Patent ApplicationSer. No. 62/448,886 filed Jan. 20, 2017, which is incorporated herein byreference.

BACKGROUND Field

Embodiments described herein generally relate to methods for formingsemiconductor devices, and more particularly to methods for forming finfield effector transistors (FinFETs).

Description of the Related Art

As circuit densities increase for next generation devices, the widths ofinterconnects, such as vias, trenches, contacts, gate structures andother features, as well as the dielectric materials therebetween,decrease to 22 nm or smaller dimensions, whereas the thickness of thedielectric layers remain substantially constant, with the result ofincreasing the aspect ratios of the features. Recently, complementarymetal oxide semiconductor (CMOS) FinFET devices have been widely used inmany logic and other applications and are integrated into variousdifferent types of semiconductor devices.

FinFET devices typically include semiconductor fins with high aspectratios in which the channel and source/drain regions for the transistorare formed thereover. A gate electrode is then formed over and alongsideof a portion of the fin devices utilizing the advantage of the increasedsurface area of the channel and source/drain regions to produce faster,more reliable and better-controlled semiconductor transistor devices.Further advantages of FinFETs include reducing the short channel effectand providing higher current flow.

To improve transistor performance, stressor materials may fillsource/drain areas, and the stressor materials may grow in source/drainareas by epitaxy. The epitaxial film is faceted by (111) planes and hasa diamond shape along the transistor channel direction. In other words,the epitaxial film may extend laterally and form facets. With thescaling down of transistors, fin pitch (distance between adjacent fins)is getting smaller. This may cause the reduction in the distance betweenan epitaxial film grown on a fin and an epitaxial film grown on anadjacent fin, which may cause adjacent epitaxial films to merge. Themerged epitaxial films decreases the effect of epitaxial films on thestrain in the transistor channel, and defects may form easily at thejunction of the merged area.

Therefore, there is a need for an improved method for forming FinFETs.

SUMMARY

Methods for forming semiconductor devices, such as FinFETs, areprovided. In one embodiment, a method includes removing a portion ofeach fin of a plurality of fins formed on a semiconductor substrate toexpose a surface of a remaining portion of each fin, wherein the surfaceis recessed from a surface of a first dielectric material formedadjacent to each fin, forming a feature on the surface of the remainingportion of each fin, filling gaps between adjacent features with asecond dielectric material, removing the features to form a plurality ofopenings in the second dielectric material, wherein the surface of theremaining portion of each fin is exposed.

In another embodiment, a method includes epitaxially forming a featureon each exposed portion of a plurality of exposed portions of asemiconductor surface, wherein the feature comprises a compoundsemiconductor material, wherein the exposed portions are separated by afirst dielectric material disposed on covered portions of thesemiconductor surface, filling gaps between adjacent features with asecond dielectric material, removing the features to form a plurality ofopenings in the second dielectric material, wherein the surface of theexposed portions of the semiconductor surface are uncovered, anddepositing a fill material within each opening.

In another embodiment, a method includes removing semiconductor pillarsto form a plurality of trenches in a dielectric material formed adjacentto the semiconductor pillars, wherein a semiconductor surface comprisinga fin material is exposed in each trench, forming a conductive source ordrain material on each exposed semiconductor surface, wherein eachsource or drain material is formed within a corresponding trench of theplurality of trenches, and forming a metal contact over each source ordrain material, wherein the metal contact and a corresponding source ordrain material are aligned within a corresponding trench of theplurality of trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the disclosurecan be understood in detail, a more particular description of thedisclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 is a perspective view of a semiconductor structure according toone embodiment described herein.

FIGS. 2A-2H illustrate a process for forming a semiconductor deviceaccording to one embodiment described herein.

FIGS. 3A-3C illustrate a process for forming a semiconductor deviceaccording to another embodiment described herein.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

DETAILED DESCRIPTION

Methods for forming semiconductor devices, such as FinFETs, areprovided. In one embodiment, a method for forming a FinFET deviceincludes removing a portion of each fin of a plurality of fins, and aremaining portion of each fin is recessed from a dielectric surface. Themethod further includes forming a feature on the remaining portion ofeach fin, filling gaps formed between adjacent features with adielectric material, removing the features, and forming a fill materialon the remaining portion of each fin. Because the shape of the featuresis controlled, the shape of the fill material can be controlled.

FIG. 1 is a perspective view of a semiconductor structure 100 accordingto one embodiment described herein. The semiconductor structure 100 mayinclude a substrate 101, a plurality of fins 102 (only two are shown,but the structure may have more than two fins), a dielectric material104 disposed between adjacent fins 102 on the substrate 101, and a gateelectrode 110 disposed on the dielectric material 104 and over a portionof each fin 102. The substrate 101 may be a bulk silicon substrate, andmay be doped with a p-type or an n-type impurity. Other substratematerials include, but are not limited to, germanium, silicon-germanium,and other similar materials. The plurality of fins 102 may be fabricatedfrom the same material as the substrate 101. The dielectric material 104may form isolation regions, such as shallow trench isolation (STI)regions, and may include silicon oxide, silicon nitride, siliconoxynitride, silicon carbonitride, or any other suitable dielectricmaterial. As shown in FIG. 1, each of the plurality of fins 102 extendsa distance above the upper surface of the dielectric material 104. Agate dielectric 108 is formed between the gate electrode 110 and theplurality of fins 102. The gate dielectric 108 facilitates electricalisolation between the gate electrode 110 and the plurality of fins 102.The gate dielectric 108 may be fabricated from silicon nitride, siliconoxide, hafnium oxide, hafnium silicon oxynitride, hafnium silicate,hafnium silicon oxide, or any other convenient gate dielectric material.The gate electrode 110 may be fabricated from polysilicon, amorphoussilicon, germanium, silicon germanium, metals, or metal alloys.

FIGS. 2A-2H illustrate a process for forming a semiconductor deviceaccording to one embodiment described herein. FIG. 2A is a side view ofthe semiconductor structure 100. The semiconductor structure 100includes the plurality of fins 102 (three are shown) extending over anupper surface 201 of the dielectric material 104 and the gate electrode110. The gate dielectric 108 and the substrate 101 are omitted forclarity. Next, as shown in FIG. 2B, a portion of each fin 102 is removedto expose a surface 202 of a remaining portion 204 of the fin 102. Theremoval of the portion of each fin 102 may be by a selective etchingprocess so the gate electrode 110 and the dielectric material 104 arenot affected. In other words, the etch chemistry is chosen such that theetch rate of the fin 102 is faster than the etch rates of the gateelectrode 110 and the dielectric material 104 since the fin 102, thegate electrode 110, and the dielectric material 104 are made ofdifferent materials. The surface 202 of the remaining portion 204 ofeach fin 102 is recessed from the upper surface 201 of the dielectricmaterial.

As shown in FIG. 2C, a feature 206, such as a pillar or a ridge, isformed on the surface 202 of the remaining portion 204 of each fin 102.In the view of FIG. 2C, the features 206 appear in the foreground, whilethe gate electrode 110 appears in the background. Prior to forming thefeatures 206, any native oxides formed on the surfaces 201 and 202 maybe removed by a pre-clean process. The features 206 may be formed in anepitaxial deposition chamber. In one embodiment, each feature 206 isformed in by first forming a nucleation layer on the surface 202 of theremaining portion 204 of each fin 102. The substrate 101 (FIG. 1) mayhave a temperature ranging from about 300 degrees Celsius to about 400degrees Celsius and the epitaxial deposition chamber may have a pressureless than about 100 Torr during the formation of the nucleation layer.The nucleation layer may have a thickness ranging from about 50Angstroms to about 100 Angstroms. After the formation of the nucleationlayers, the substrate 101 (FIG. 1) is heated to a temperature rangingfrom about 500 degrees Celsius to about 600 degrees Celsius, thepressure of the epitaxial deposition chamber is reduced to from about 10Torr to about 40 Torr, and the features 206 are formed. The materialsused to form the nucleation layers and the features 206 include groupIII-V semiconductor materials such as GaAs, InGaAs, InAs, GaP, InP,InGaP, GaSb, InSb, GaAsSb, InAsSb, and other suitable materials. In someembodiments, group II-VI semiconductor materials may be used to form thefeatures 206. Unlike the silicon or germanium based stressor materials,which form a diamond shape due to the different growth rate on differentsurface planes, the materials used to form the features 206 do not forma diamond shape. The height, width and facets of the features 206 can becontrolled by temperature, pressure and/or precursor flow. As shown inFIG. 2C, each feature 206 may have a rectangular cross-section and asubstantially constant width W₁ over the surface 201 of the remainingportion 204 of each fin 102. The width W₁ may be greater than a width W₂of the remaining portion 204 of the fin 102. In one embodiment, thewidth W₁ is about 1 nm to about 10 nm wider than the width W₂.

Next, as shown in FIG. 2D, a dielectric material 208 is formed betweenadjacent features 206. In one embodiment, the dielectric material 208and the features 206 are coplanar at the end of the deposition processof the dielectric material 208. In another embodiment, the dielectricmaterial 208 is also formed on the features 206 and the gate electrode110. The dielectric material 208 may be the same material as thedielectric material 104. In one embodiment, the dielectric material 208is silicon oxide and is deposited by a flowable chemical vapordeposition (FCVD) process. A chemical mechanical planarization (CMP)process is then performed on the dielectric material 208 to expose thefeatures 206, as shown in FIG. 2E. A surface 210 of each feature 206 isexposed, and the surfaces 210 are coplanar with a surface 212 of thedielectric material 208.

Next, as shown in FIG. 2F, the features 206 are removed to expose thesurfaces 202 of the remaining portions 204. The gate dielectric 108 andthe gate electrode 110 should appear in the background but are omittedfor clarity. The features 206 may be removed by a selective etchingprocess so the dielectric material 208 is not affected. In other words,the etch rate of the feature 206 is much faster than the etch rate ofthe dielectric material 208 since the feature 206 and the dielectricmaterial 208 are made of different materials. As the result of theremoval process, a plurality of openings 214, such as trenches or vias,is formed in the dielectric material 208. Each opening 214 has the sameshape as the feature 206. A fill material 216, such as a stressormaterial, is then deposited in each opening 214 on the surface 202 ofthe remaining portion 204 of each fin 102, as shown in FIG. 2G. The fillmaterial may be also deposited on the surface 212 of the dielectricmaterial 208, and an etch back process may be performed to remove thefill material deposited on the surface 212 of the dielectric material208. The fill material 216 may be the source or drain of a FinFET deviceand may be a silicon and/or germanium based material. In one embodiment,the fill material 216 is an electrically conductive material. The fillmaterial 216 may be formed by an epitaxial deposition process in anepitaxial deposition chamber available from Applied Materials, Inc. Theepitaxial deposition process is generally performed by flowing epitaxyprecursors such as silane, germane, phosphine, and arsine into theepitaxial deposition chamber and heating the substrate to a temperature,for example 300 degrees Celsius to 600 degrees Celsius, that results inepitaxial deposition on the substrate. For the group III-V semiconductormaterials, precursors for the group III elements include halides, whichcan be reacted with materials such as arsine, phosphine, and stilbene.In one embodiment, the fill material 216 is silicon doped withphosphorus and the FinFET device is an n-type FET. In anotherembodiment, the fill material 216 is silicon germanium doped with boronor gallium, and the FinFET device is a p-type FET. The shape of the fillmaterial 216 is constrained by the opening 214 that the fill material216 is formed therein. Thus, instead of having a diamond shape, the fillmaterial 216 has a rectangular cross-section, and the distance betweenadjacent fill materials 216 is increased. Each fill material 216 has asurface 213 that is recessed from the surface 212 of the dielectricmaterial 208.

Another benefit of forming the plurality of openings 214 is that anymaterial deposited on the surface 213 of the fill material 216 withinthe opening 214 is self-aligned. In one embodiment, a metal contact 222is deposited over the fill material 216 within the opening 214, as shownin FIG. 2H. The metal contact 222 is self-aligned to the fill material216, i.e., a source or drain, since both the metal contact 222 and thefill material 216 are formed within the opening 214. The metal contact222 may be fabricated from a metal such as cobalt or tungsten.Additional materials may be formed on the fill material 216 prior to thedeposition of the metal contact 222. For example, a silicide orgermanide layer 218 may be formed on the fill material 216 by asilicidation process. A liner 220 may be formed conformally in theopening 214 by an atomic layer deposition (ALD) process. The metalcontact 222 is then deposited on the liner 220. A CMP process may beperformed to planarize the surface.

FIGS. 3A-3C illustrate a process for forming a semiconductor deviceaccording to another embodiment described herein. FIG. 3A is a side viewof the semiconductor structure 300. The semiconductor structure 300includes a substrate 302 having a semiconductor surface 305. Thesemiconductor surface 305 includes a plurality of exposed portions 304separated by a plurality of covered portions 306. In one embodiment, thesubstrate 302 is a silicon substrate, and the semiconductor surface 305is a silicon surface. A first dielectric material 308 is disposed on thecovered portions 306 of the semiconductor surface 305. The firstdielectric material 308 may be silicon oxide, silicon nitride, siliconoxynitride, silicon carbonitride, or any other suitable dielectricmaterial. Next, as shown in FIG. 3B, a feature 310 is formed on eachexposed portion 304 of the semiconductor surface 305. The features 310may be the same as the features 206. Prior to forming the features 310,any native oxides formed on the semiconductor surface 305 may be removedby a pre-clean process. The features 310 may be formed in an epitaxialdeposition chamber. In one embodiment, each feature 310 is formed in byfirst forming a nucleation layer on a corresponding exposed portion 304of the semiconductor surface 305. The nucleation layer and the features310 may be formed under the same process conditions as the nucleationlayer and the features 206. Unlike the silicon or germanium basedmaterials, which form a diamond shape due to the different growth rateon different surface planes, the materials used to form the features 310do not form a diamond shape. The height, width and facets of thefeatures 310 can be controlled by temperature, pressure and/or precursorflow.

Next, as shown in FIG. 3C, a second dielectric material 312 is formedbetween adjacent features 310. In one embodiment, the second dielectricmaterial 312 and the features 310 are coplanar at the end of thedeposition process of the second dielectric material 312. In anotherembodiment, the second dielectric material 312 is also formed on thefeatures 310 and a CMP process is performed on the second dielectricmaterial 312 to expose the features 310. The second dielectric material312 may be the same material as the dielectric material 208.

Process steps shown in FIGS. 2F, 2G and 2H are then performed on thesemiconductor structure 300 to form a plurality of openings in thesecond dielectric material 312, to deposit a fill material in theplurality of openings, and to deposit a metal in the plurality ofopenings. The fill material may be the same as the fill material 216,and the metal may be the same as the metal contact 222. The fillmaterial and the metal are self-aligned since both materials are formedwithin the same opening.

While the foregoing is directed to embodiments of the disclosure, otherand further embodiments may be devised without departing from the basicscope thereof, and the scope thereof is determined by the claims thatfollow.

1. A method, comprising: removing a portion of each fin of a pluralityof fins formed on a semiconductor substrate to expose a surface of aremaining portion of each fin, wherein the surface is recessed from asurface of a first dielectric material formed adjacent to each fin;forming a feature on the surface of the remaining portion of each fin;filling gaps between adjacent features with a second dielectricmaterial; and removing the features to form a plurality of openings inthe second dielectric material, wherein the surface of the remainingportion of each fin is exposed.
 2. The method of claim 1, furthercomprising forming a fill material on the surface of the remainingportion of each fin, wherein each fill material is formed within acorresponding opening of the plurality of openings.
 3. The method ofclaim 1, wherein the features are formed in an epitaxial depositionchamber.
 4. The method of claim 1, wherein the features are removed by aselective etching process.
 5. The method of claim 2, wherein the fillmaterial is formed in an epitaxial deposition chamber.
 6. The method ofclaim 1, wherein each feature is fabricated from a group II I-Vsemiconductor material or a group II-VI semiconductor material.
 7. Themethod of claim 1, wherein each feature has a first width and each finhas a second width, wherein the first width is greater than the secondwidth.
 8. A method, comprising: epitaxially forming a feature on eachexposed portion of a plurality of exposed portions of a semiconductorsurface, wherein the feature comprises a compound semiconductormaterial, wherein the exposed portions are separated by a firstdielectric material disposed on covered portions of the semiconductorsurface; filling gaps between adjacent features with a second dielectricmaterial; removing the features to form a plurality of openings in thesecond dielectric material, wherein the exposed portions of thesemiconductor surface are uncovered; and depositing a fill materialwithin each opening.
 9. The method of claim 8, further comprisingperforming a pre-clean process on the exposed portions of thesemiconductor surface prior to forming the features.
 10. The method ofclaim 8, wherein the features are formed in an epitaxial depositionchamber.
 11. The method of claim 8, wherein the features are removed bya selective etching process.
 12. The method of claim 8, wherein the fillmaterial is formed in an epitaxial deposition chamber.
 13. The method ofclaim 8, wherein the fill material comprises a semiconductive materialor a conductive material.
 14. A method, comprising: removingsemiconductor pillars to form a plurality of trenches in a dielectricmaterial formed adjacent to the semiconductor pillars, wherein asemiconductor surface comprising a fin material is exposed in eachtrench; forming a conductive source or drain material on each exposedsemiconductor surface, wherein each source or drain material is formedwithin a corresponding trench of the plurality of trenches; and forminga metal contact over each source or drain material, wherein the metalcontact and a corresponding source or drain material are aligned withina corresponding trench of the plurality of trenches.
 15. The method ofclaim 14, further comprising forming a silicide or germanide layer oneach source or drain material prior to forming the metal contact overeach source or drain material.
 16. The method of claim 15, furthercomprising forming a liner on the silicide or germanide layer prior toforming the metal contact over each source or drain material.
 17. Themethod of claim 16, wherein the metal contact is formed on the liner.18. The method of claim 16, wherein the metal contact comprises cobaltor tungsten.
 19. The method of claim 14, wherein the semiconductorpillars are removed by a selective etching process.
 20. The method ofclaim 14, wherein the source or drain material is formed in an epitaxialdeposition chamber.